1. Field of the Invention
The present invention relates to the construction of combinational logic circuits, and more particularly to lookahead adder circuits.
2. Discussion of the Related Art
Conventional combinational circuits, and particularly adders, are constructed with logic gates. These logic gates are often connected in a cascade arrangement, which increases calculating time, since the output of each gate is valid only when the outputs of its preceding gates are valid.
Generally, to construct an adder, elementary adders are connected in a cascade arrangement, where a carry input of each elementary adder is connected to a carry output of its preceding elementary adder. The carry calculating time is a critical parameter since the result of a cascade adder, including its carry output, is valid only when the preceding adder supplies it with a valid carry input.
The fastest adders, such as TTL circuits '83 and '283 (4-bit adders), perform an anticipated carry calculation (lookahead). In these adders, the carry output is calculated independently from the bit-to-bit additions, the circuit directly combining the inputs. Thus, the carry calculation is performed at essentially the same time as the bit-to-bit additions.
The calculating time for the carry is determined by the longest path traveled by the signals from the inputs to the carry output. This path includes logic gates arranged in a number of logic layers, one logic layer including elementary logic gates having their inputs supplied by the outputs of elementary gates from the preceding layer. Each logic layer brings in the propagation delay of an elementary gate. Adders '83 or '283 include four logic layers for the carry output. Their entire circuit is a complex circuit including 232 transistors.
The 8-bit or 16-bit adders are generally constructed with 4-bit adders connected in a cascade arrangement, since it is more advantageous than making an 8-bit or 16-bit lookahead circuit.